1. Field of the Invention
The present invention relates to synchronous semiconductor memory devices, and more particularly, to a synchronous burst static random access memory (abbreviated as "BSRAM" hereinafter) including an address input register.
2. Description of the Background Art
In these few years, it is common to arrange a cache memory between a microprocessor and the main memory to increase the speed of the computer system. A BSRAM operating in synchronization with an external clock signal is widely used as a cache memory.
FIG. 8 is a block diagram schematically showing a conventional BSRAM. Referring to FIG. 8, this BSRAM 1 includes a memory cell array 2, a clock buffer 3, an address buffer 4, a predecoder 5, an address input register 6, a decoder 7, and an input/output (I/O) buffer 8. For the sake of simplification, only the circuits related to the 2 bits of external address signals EA0 and EA1 are shown in FIG. 8, representative thereof. In practice, many more bits of external address signals are applied.
FIG. 9 is a timing chart showing an operation of the BSRAM of FIG. 8. Referring to FIG. 9, clock buffer 3 generates complementary internal clock signals .phi.1 and .phi.2 in response to an external clock signal CLK. External address signals EA0 and EA1 are applied during an H (logical high) level of internal clock signal .phi.1. Address buffer 4 generates complementary internal address signals A0, A1 and /A0, /A1 in response to external address signals EA0 and EA1. Here, there is a delay time D1 from the input of external address signals A0 up to the generation of internal address signal /A0. Then, predecoder 5 generates predecode signals /A1.cndot./A0, /A1.cndot.A0, A1.cndot./A0, A1.cndot.A0 in response to internal address signals A0, /A0, A1, /A1. Here, there is a delay time D2 from the generation of internal address signal /A0 up to generation of predecode signals /A1.cndot./A0. Since internal clock signal .phi.1 is now at an H level, predecode signals /A1.cndot./A0, /A1.cndot.A0, A1.cndot./A0, A1.cndot.A0 are latched in latch circuits 61-64 located as the former stage of address input register 6. In response to a rise of internal clock signal .phi.2, predecode signals /A1.cndot./A0, /A1.cndot.A0, A1.cndot./A0, A1.cndot.A0 latched in latch circuits 61-64 are latched at the latter stage of latch circuits 65-68, respectively. Address input register 6 provides these latched predecode signals /A1.cndot./A0, /A1.cndot.A0, A1.cndot./A0, A1.cndot.A0 to decoder 7.
In order to reliably latch predecode signals /A1.cndot./A0 in latch circuit 65, the latch of predecode signals /A1.cndot./A0 by latch circuit 61 must be completed before internal clock signal .phi.2 is pulled up. More specifically, a set up time tsu (reg) of address input register 6 is required from the generation of predecode signals /A1.cndot./A0 up to the rise of internal clock signal .phi.2. This means that the total of the above delay times D1 and D2 and the set up time tsu (reg) of address input register 6 is at least required for the set up time ts of external address signal A0. More specifically, ts.gtoreq.D1+D2+tsu (reg).
When the input of external address signals EA0 and EA1 is delayed so that the time starting from the input of external address signals EA0 and EA1 up to the rise of internal clock signal .phi.2 becomes shorter than set up time ts, latch circuits 65-68 will not be able to latch predecode signals /A1.cndot./A0, /A1.cndot.A0, A1.cndot./A0, A1.cndot.A0. As a result, address input register 6 will not be able to output the proper signals.
A redundancy circuit that substitutes a defective memory cell with a spare memory cell is provided to improve the yield in a RAM. The above-described set up time is also required for such a redundancy circuit. There is a problem that the redundancy circuit will not operate properly if the input of an external address signal is delayed.
U.S. Pat. No. 5,086,414 disclosing a memory including two stages of latch circuit is completely silent about the redundancy circuit.